Lab 1 AI Prototype

Write Me HDL

Learning Goals

The goal of this prototype is to experiment with using AI as a coding assistant to generate HDL. By the end of this experiment you should be able to:

  • Demonstrate how an LLM can be used as a coding partner.
  • Analyze the quality of the LLM-generated RTL.
  • Document specific tips on how to use the LLM effectively.

The question you should be interrogating is “can my LLMs of choice generate SystemVerilog that compiles, synthesizes and exhibits correct behavior?”“

Note that performance varies a great deal among LLMs. If you want a subscription-grade model, the college provides Gemini Pro Models as part of the Google Suite for Education, and Copilot as part of Microsoft 365. It is also easy to secure Copilot access through a free educational license. You might see better performance with frontier models (the latest Anthropic and OpenAI models), but do not feel obligated to pay for them; you are not graded on the quality of your LLM output, but rather on your reflection.

Prototype

Fire up your favorite LLM. Enter the prompt below.

NoteLLM Prompt

Write SystemVerilog HDL to leverage the internal high speed oscillator in the Lattice UP5K FPGA and blink an LED at 2 Hz. Take full advantage of SystemVerilog syntax, for example, using logic instead of wire and reg.

Create a new Radiant project, type the code generated by the LLM in and analyze the results. If the synthesis fails, type the error message back into the LLM to see what suggestions it generates.

Reflect

Write up a few paragraphs reflecting on your experience using the LLM to help you code. Feel free to make full use of screenshots, code snippets, and other media as you write your reflections, though spoiler non-essential figures to make reading easier. Similarly, if you choose to include the full transcript of your session, then use spoiler tags to hide it so that instructors can read your reflection easily.

Here are a few ideas of on what you might comment on:

  • How would you rate the quality of the output and why?
  • What SystemVerilog constructs/syntax did the LLM generated that were new to you?
  • Did the LLM-generated code synthesize the first time around? If not, what were the issues?
  • What error or warning messages did Radiant output?
  • What would you do differently the next time you use an LLM in your workflow?