Lab 1: FPGA and MCU Setup and Testing

Introduction

In this lab you will familiarize yourself with the microcontroller unit (MCU) and field-programmable gate array (FPGA) development boards we will be using this semester.

Learning Objectives

By the end of this lab you will have…

  • Assembled your development board for the class and tested out your MCU and FPGA boards.
  • Written a Verilog module to control LEDs and a 7-segment display.
  • Programmed the FPGA with Verilog code.
  • Gained confidence in building, assembling, testing, and debugging circuits.
  • Interfaced a 7-segment display to the board.

Requirements

Follow the steps in this guide to test your FPGA and MCU boards. Write some Verilog code to exercise the FPGA using the switches, LEDs, and a 7-segment display to ensure your board is operational. Simulate and synthesize your code, then upload it to the flash memory and re-test the board. Hook up a 7-segment display and demonstrate that it works.

How This Lab Is Organized

The step-by-step tool instructions for this lab live in the tutorials section of the website rather than in this page, so that you can find them again later in the semester without digging through Lab 1.

This lab has three parts. Do them in order.

  1. Work through the tutorials to set up your tools, build and test your board, and learn the Radiant and QuestaSim workflow.
  2. Design the system described in this page.
  3. Build, simulate, and test your design on the board.

Part 1: Tutorials

Work through these tutorials in order. Each one is self-contained. Read it end to end and follow along. A “Working on Lab 1?” box at the bottom of each tutorial sends you back here.

  1. Hardware Background: important programming instructions and background information for the FPGA and MCU. You should also familiarize yourself with the documentation for both the UPduino v3.1 and Nucleo-L432KC boards. The website has links for the UPduino v3.1 User Guide and the Nucleo-L432KC User Manuals on the Resources tab. These two documents contain information that will be helpful for answering questions that you may have during the course of this lab.
  2. Creating and Initializing Your Git Repo video: the first step before you begin writing any code is to create a Git repository. If you are new to Git, the Git Setup tutorial covers the basics first.
  3. Lattice Radiant Installation: Lattice Radiant (includes QuestaSim/ModelSim) for FPGA design.
  4. SEGGER Embedded Studio Setup: SEGGER Embedded Studio for MCU development.
  5. Lattice Radiant iCE40 UltraPlus Project Setup: build the blinking-LED demo from start to finish. This covers creating a project, synthesizing, assigning pins, and programming the board.
  6. E155 Development Board Assembly: assemble your development board, then work through the Testing the Boards section. The majority of your time on this lab will likely be spent assembling the board, so make sure to plan ahead.
  7. QuestaSim/ModelSim Simulation: simulate by forcing signals, then write and run testbenches.
  8. Seven-Segment Displays: how common anode displays work and how to wire one.
NoteCheckpoint: test your boards

Before writing any of your own HDL, confirm that both halves of your assembled board work using Testing the Boards from tutorial 6. You will program the FPGA with a provided design that toggles a pin at about 1 Hz, then program the MCU1 with a provided program that reads that pin and echoes it back, which verifies both devices and the communication between them.

Hold on to the FPGA test project — you will reuse its clock generation code in your own design below.

Part 2: Design

Now it’s your turn to write some Verilog! Design a set of Verilog modules (see the specs for a required structure) to operate a 7-segment display and some on-board LEDs. The top-level Verilog module should have the following inputs and outputs:

Signal Name Signal Type Description
s[3:0] input the four DIP switches (on the board, SW6)
reset_b input active low input that resets all sequential state, map it to a button on the motherboard
led[2:0] output 3 LEDs (you may use the on-board LEDs)
seg[6:0] output the segments of a common-anode 7-segment display
ImportantThe clock is not a top-level port

Notice that there is no clk input in the table above. The 48 MHz clock is generated inside the FPGA by the HSOSC primitive, which you instantiate in your top-level module. The clock is therefore an internal signal, not a pin you route in from outside.

This matters when you write your testbenches: a module that takes clk as an input port (like your counter) can be given a generated clock by its testbench, but your top-level testbench has to let the real HSOSC produce the clock.

The following tables define the relationship of the LEDs to the switches and clock.

S1 S0 led[0]
0 0 OFF
0 1 ON
1 0 ON
1 1 OFF
S3 S2 led[1]
0 0 OFF
0 1 OFF
1 0 OFF
1 1 ON
led[2]
Blink at 2.4 Hz

The 7-segment display should display a single hexadecimal digit specified by s[3:0]. Be sure each digit can be distinguished from other digits (e.g., b and 8 should look different).

Remember that you will be using a common anode display. The anode (positive terminal) of all of the LEDs is tied to 3.3 V through a single (“common”) pin. Each segment’s cathode (negative terminal) is connected to a pin. Therefore, you will need 7 separate control signals. Remember that a logic 0 applied to the cathode will turn on the segment. The segments are defined as shown below. Let seg[0] be A and seg[6] be G.

Seven-segment display segment mapping
Figure 1: Seven-segment display pin map
TipClock Generation

To generate the clock for your design, use the onboard high-speed oscillator. This is the same strategy as in the FPGA testing source code you downloaded when you tested your boards. If you look at that Verilog code, you’ll notice an instantiated module called HSOSC (for High-Speed OSCillator). This module is part of the iCE40 Technology Library (see the iCE40 Technology Library document linked on the course website) and is a built-in module included with Lattice Radiant designed for controlling the internal oscillator on the iCE40 chip. You can simply copy the line from the testing program and use it in your project.

Part 3: Build, Simulate, and Test

Work through the Building, Simulating, and Testing an FPGA Design tutorial end to end and follow along with your own design. A “Working on Lab 1?” box at the bottom sends you back here. It covers these steps in order:

  1. Create the Project: set up a UP5K project and add your lab1_xx.sv source file.
  2. Logic Simulation in ModelSim: force the inputs by hand and check the led and seg outputs.
  3. Automatic Testing with a Testbench: write stim/assert testbenches for each submodule and the top level.
  4. Pin Assignment: map your signals to FPGA pins and enable pull-ups on s[3:0].
  5. Seven Segment Display Circuit: wire the display with current-limiting resistors.
  6. Generating the FPGA Configuration Files: synthesize, then check the RTL schematic and resource usage.
  7. Program and Test Your Design: program the flash and re-test the board against the design above.

AI Prototype and Reflection

Don’t forget to complete the AI Prototype and reflect on it in your lab 1 writeup.

What to Submit

See the Lab 1 specifications for the full list of deliverables and how this lab is graded.

Share Your Feedback

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Footnotes

  1. In order for the NUCLEO board to be compatible with SEGGER, it is necessary to reflash the ST-LINK programmer with SEGGER J-Link firmware to convert it to a J-Link. This has been already taken care of on the board in your kit, but if you want to use another STM32 board with SEGGER you’ll need to follow the instructions in Appendix B of the SEGGER Embedded Studio Setup tutorial to do this yourself.↩︎